Abstract: The rapid advancement of artificial intelligence is being fueled by ever‑increasing demands on compute and memory, resulting in soaring power consumption and performance bottlenecks. A major contributor is the cost of data movement between compute and memory, which limits efficiency and scalability. While current industry approaches largely rely on reduced‑precision arithmetic, model sparsity, and software‑level optimizations, these methods do not address the underlying device‑level challenges.
In this talk, I will highlight key materials and device‑engineering innovations that enable intrinsic reductions in transistor power, increased storage bit density and bandwidth, as well as lower memory‑access latency. The discussion will focus on technology pathways that leverage tight integration and co‑optimization of diverse unit processes, many of which serve as foundational building blocks for advanced Si CMOS and DRAM platforms.
Bio: Milan D. Pešić received a M.Sc. and Ph.D. Electrical Engineering from the Technical University of Dresden, Germany. He is currently Director of Technology Pathfinding at Applied Materials Inc, Santa Clara USA. He is leading a device pathfinding and overseeing device and cell physics and research activities in the field of advanced logic, (emerging) (non)volatile memories and devices. Previously, he was with MDLSoft Inc., Santa Clara, USA, Ferroelectric Memory Company, Dresden, and NaMLab, Dresden. Up to now, he has given 20 invited talks and courses at major electron-devices conferences (IEDM, VLSI, IRPS, etc.) and (co)authored over 90 technical papers, five book chapters, and filed over 40 patents.