With the slowing of Moore's law, computer architects have turned to domain-specific hardware accelerators to improve the performance and efficiency of computing systems. However, programming these systems entails significant modifications to the software stack to properly leverage the specialized hardware. Moreover, the accelerators become obsolete quickly as the applications evolve. What is needed is a structured approach for generating programmable accelerators and for updating the software compiler as the accelerator architecture evolves with the applications. In this talk, I will describe a new agile methodology called AHA for co-designing programmable hardware accelerators and compilers. Our methodology employs a combination of new programming languages and formal methods to automatically generate the accelerator hardware and its compiler from a single specification. This enables faster evolution and optimization of accelerators, because of the availability of a working compiler. I will showcase this methodology using three generations of coarse-grained programmable accelerator chips that we designed using this flow: (1) Amber, that targets dense image processing and machine learning, (2) Onyx, that optimizes dense performance over Amber and additionally supports sparse tensor algebra and finally (3) Opal, that further optimizes for sparse machine learning applications.
Agile Design of Domain-Specific Hardware Accelerators and Compilers
Abstract
Bio
Priyanka Raina received the B.Tech. degree in Electrical Engineering from IIT Delhi in 2011, and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from MIT in 2013 and 2018, respectively. She was a Visiting Research Scientist with NVIDIA Corporation in 2018. Since 2018 she is an Assistant Professor of Electrical Engineering at Stanford University, where she works on domain-specific hardware architectures and agile hardware–software codesign methodology. Dr. Raina is a 2018 Terman Faculty Fellow. She was a co-recipient of the Best Demo Paper Award at VLSI 2022, the Best Student Paper Award at VLSI 2021, the IEEE Journal of Solid-State Circuits (JSSC) Best Paper Award in 2020, the Best Paper Award at MICRO 2019, and the Best Young Scientist Paper Award at ESSCIRC 2016. She has won the DARPA Young Faculty Award in 2024, Sloan Research Fellowship in 2024, the National Science Foundation (NSF) CAREER Award in 2023, the Intel Rising Star Faculty Award in 2021, and the Hellman Faculty Scholar Award in 2019. She was the Program Chair of the IEEE Hot Chips in 2020. She serves as an Associate Editor for the IEEE Journal of Solid-State Circuits and IEEE Solid-State Circuits Letters.