Thinking Outside the Die: Trillion Transistor Chips for the ML Accelerator of the Future.
MTL Seminar Series
Sean Lie, Cerebras
Speaker
Abstract
ML models are growing at an unprecedented rate and traditional forms of scaling chip performance are insufficient to keep up. In this talk, we will examine how co-design can enable specialized ML architectures including wafer-scale chips, sparse computation, optimized memories, and interconnects. We will explore this rich design space using the Cerebras architecture as a case study, highlighting design principles that enable the ML models of the future.