Analog-to-digital converters (ADCs) are essential in modern electronics. The advances in integrated circuits (IC) technology have improved the digital signal processing significantly, bringing the ADC performance limitations to the forefront. The performance of high-speed ADCs is often limited by clock jitter. In this work, we have designed a 1-GHz CT pipeline ADC with state-of-the-art performance and demonstrated improved tolerance to clock jitter.
A 1-GHz Bandwidth CT Pipelined ADC with Reduced Sensitivity to Clock Jitter
MTL Seminar Series
Rishabh Mittal, DDS
Abstract
Bio
Rishabh Mittal received the Ph.D. degree from MIT in Feb. 2023. Since March 2023, he has been with MediaTek, Woburn, MA, USA, where he is developing linearization techniques for wideband receivers. His interests are in the area of analog circuit design with a focus on high-speed data converters.