Disruptive Material Research for the Next Generation Semiconductors at SAIT

Special MTL Seminars
Dr. Jinseong Heo
Grier Room (34-401)
Open to
MTL Community

Abstract: In this presentation, I aim to introduce the material research conducted at SAIT, focusing on its direct implication to disruptive semiconductor devices. Firstly, as we confront the limitations posed by the lateral scaling in three prominent product categories: Logic, DRAM, and Flash, our efforts are dedicated to the development of innovative materials capable of surpassing these constraints, thereby shaping the trajectory of future advancements. The overarching motif underpinning our material research for these revolutionary devices centers around the concept of three-dimensional integration for individual components, coupled with their hetero-integration, aimed at enhanced performance and minimal energy consumption. To achieve the 3D scheme, several ongoing projects are focused on various materials spanning from high-k dielectric to oxide semiconductors and metal interconnect. Specifically, I will discuss our recent progress in comprehending the fundamentals of ferroelectric materials for logic and memory applications.

Given the escalating power density, which results in inevitable heat dissipation in logic devices, we demonstrate that leveraging the negative differential capacitance of ferroelectric hafnia in ultrathin limit in the gate stack of a logic transistor has the potential to reduce power consumption by 30%. This reduction is achieved through gate capacitance enhancement. We propose the incorporation of ferroelectric material as a fundamental solution to address the thermal challenge, thereby playing a pivotal role in the architecture of 3D stack FETs.

Additionally, as the conventional planar transistor within the DRAM cell is poised to be substituted by a vertical counterpart in the near future, aiming for a more compact 4F2 cell size, it will soon encounter the limits of 2D scaling. Consequently, the most sought-after solution will be the ultimate capless DRAM in 3D arrangement.

On the other hand, vertical NAND, initially introduced to the market by Samsung in 2013, has progressed by stacking more layers. However, the increased challenges related to high-aspect-ratio etching and structural stability have rendered additional stacking more difficult. This calls for the exploration of new device schemes to overcome these challenges and facilitate further stacking.

As one of the candidates for 3D DRAM and ultimate vertical NAND, I will present a three-terminal ferroelectric FET that shows an unprecedented sub-ns switching speed. This feature makes it applicable to vertical DRAM as well as advanced VNAND. Due to efficient polarization switching replacing high-voltage charge tunneling, a ferroelectric FET that utilizes lower voltage to store multi-bit information within a cell enables vertical scaling of a cell in vertical NAND. Furthermore, this presentation will introduce two-terminal ferroelectric diodes with a high rectification ratio and ferroelectric tunnel junctions with high uniformity. The two-terminal devices aim to enhance endurance and also facilitate neuromorphic applications. Lastly, the envisioning of 3D hetero-integration of individual components will be discussed.

Bio: Dr. Jinseong Heo is a Master (Vice President of Technology) and the Semiconductor Material Theme Leader of Samsung Advanced Institute of Technology (SAIT). His research scope has covered various materials spanning from high-k dielectric to oxide semiconductors and magnetic materials for disruptive semiconductor devices since he joined SAIT in 2008. Dr. Heo is a recipient of Samsung Electronics Best Engineer and Best Patent awards in 2020. In 2020 and 2012, he was also awarded “The Best Paper” in Samsung Best Paper Award in recognition of his material and device research for disruptive semiconductor technologies. He is an inventor of over 130 issued US patents and an author of >45 articles in peer-reviewed journals. He received his B.S. from Korea Advanced Institute of Science and Technology in the department of physics, his M.S. and his Ph.D. from California Institute of Technology in 2004 and 2008, respectively, in the department of applied physics.