Integration via the 3rd Dimension

The Future of Nanoscale Electronics Symposium
Paolo Gargini, IEEE, Chairman IRDS


During the preparation of the 2013 International Technology Roadmap for Semiconductors (ITRS), it was assessed that horizontal (2D) features were going to be approaching the range of a few nanometers shortly beyond 2020 and so it became clear that the semiconductor industry was going to be running out of horizontal space by then! The question was: “Which products were going to be reaching these 2D limits first?” Memory products have always been the leaders in transistor density (i.e., smallest feature pitch) and so it should have not been surprising to realize that the solution to this problem was to come first from companies producing Flash memories. In fact, multiple Flash producers announced in 2014 that future products were going to fully utilize the vertical dimension. Flash products with as many as 64 layers of transistors have already been introduced into manufacturing. It is expected that logic producers will also soon adopt an approach that fully utilizes the benefits of the vertical dimension. The International Roadmap for Devices and Systems (IRDS) has identified this third phase of the semiconductor industry as: 3D Power Scaling. The goal of the presentation is to outline the challenges and accomplishments of this new approach to further extend Moore’s Law for at least another 15 years.