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Tsu-Jae Liu holds a Ph.D. in Electrical Engineering from Stanford University and presently is the TSMC Distinguished Professor in Microelectronics at the University of California, Berkeley. Her research contributions include the FinFET transistor design which enabled CMOS technology scaling to below 25 nm.
As the minimum feature size of an integrated circuit has been scaled down well below the wavelength of light used in the photolithographic process, the semiconductor industry has faced a growing challenge of continuing to increase the density of transistors at ever lower cost per transistor. This talk will describe a cost-effective method for defining sub-lithographic features, to help extend the era of Moore’s Law.