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Anthony (Tony) Yen began working on nanopatterning as a graduate student at MIT's Nanostructures Laboratory under the guidance of Prof. Hank Smith. After graduation in 1991, he did R&D work on optical microlithography at Texas Instruments and, as a TI assignee, at IMEC. Activities there included early work on optical proximity correction which he and his TI colleagues later applied to the production of Sun microprocessors. He joined Taiwan Semiconductor Manufacturing Company in 1997 to lead its newly formed lithography R&D group. From 2001 to 2003 he was on assignment at SEMATECH where he co-led its lithography division to build infrastructure for next-generation lithography technologies. He then joined Cymer Inc. as senior vice president of marketing but returned to TSMC at the end of 2006. He was put in charge of developing EUV lithography shortly thereafter and is currently director of Nanopatterning Technology Infrastructure Division. Yen received his BSEE degree from Purdue University and his SM, EE, PhD, and MBA degrees from MIT. He has over 80 publications and 40 US patents on nanopatterning. He is a fellow of SPIE and a past chair of its advanced lithography symposia.
Thirty years have passed since the very first results of EUV imaging were made public by Kinoshita and co-workers of NTT Japan. Why does it take this long for EUVL to develop from infancy to near maturity? First, there was still quite a bit of headroom left in optical lithography back then, making the switch to a next-generation lithography technology less urgent, until now. Second, technological barriers that had to be surmounted in order to put EUVL in high-volume manufacturing have indeed been high. In this presentation, I will review the early history of EUVL, point out how its life was extended beyond the initial phase of promising results, and present some most recent progress on the performance of its exposure tools, technology infrastructure, and patterning capability, and hopefully convince the audience that the technology is crossing the threshold to become a mainstream patterning technology for sub-10-nm generations of integrated circuits.