April 27, 2018
The Future of Nanoscale Electronics Symposium

Integration via the 3rd Dimension

Paolo Gargini, IEEE, Chairman IRDS
  • Abstract
  • Biography

During the preparation of the 2013 International Technology Roadmap for Semiconductors (ITRS), it was assessed that horizontal (2D) features were going to be approaching the range of a few nanometers shortly beyond 2020 and so it became clear that the semiconductor industry was going to be running out of horizontal space by then! The question was: “Which products were going to be reaching these 2D limits first?” Memory products have always been the leaders in transistor density (i.e., smallest feature pitch) and so it should have not been surprising to realize that the solution to this problem was to come first from companies producing Flash memories. In fact, multiple Flash producers announced in 2014 that future products were going to fully utilize the vertical dimension. Flash products with as many as 64 layers of transistors have already been introduced into manufacturing. It is expected that logic producers will also soon adopt an approach that fully utilizes the benefits of the vertical dimension. The International Roadmap for Devices and Systems (IRDS) has identified this third phase of the semiconductor industry as: 3D Power Scaling. The goal of the presentation is to outline the challenges and accomplishments of this new approach to further extend Moore’s Law for at least another 15 years.

Dr. Paolo Gargini was Director of Technology Strategy at Intel in Santa Clara, California. While at Intel, he was also responsible for worldwide research activities conducted by universities and consortia for the benefit of the Technology and Manufacturing Group. At the end of 2012 Dr. Paolo Gargini returned to the world of research (e.g., ITRS, IEUVI, ICCI, Stanford University and other organizations) after having worked for 34 years at Intel Corporation.

Dr. Gargini received a doctorate in Electrical Engineering in 1970 and a doctorate in Physics in 1975 from the Università di Bologna, Italy. He has done research at LAMEL in Bologna, Stanford Electronics Laboratory, and Fairchild Camera and Instrument Research and Development in Palo Alto from 1970 to 1977. Since joining Intel in 1978, Dr. Gargini conducted studies on Process Reliability; he was responsible for developing the building blocks of HMOS III and CHMOS III technologies used in the 1980’s for the 80286 and the 80386 processors. In 1985 he headed the first submicron process development team at Intel.

In 1995, Dr. Gargini was elevated to Intel Fellow. Dr. Gargini has been the Chairman of the Executive Steering Council (ESC) of I300I and, subsequently, of International Sematech from 1996 to 2000. He was then a member of the Sematech Board until 2012. In 1998, Dr. Gargini became the Chairman of the International Technology Roadmap for Semiconductors (ITRS). He also headed the International EUV Initiative (IEUVI) and the International Consortia Cooperation Initiative (ICCI). Dr. Gargini became the first Chairman of the Governing Council of the Nanoelectronics Research Initiative (NRI) funded in June 2005 by SIA. Dr. Gargini was inducted in the VLSI Research Hall of Fame in 2009. Dr. Gargini was elevated to Fellow of the Japan Society of Applied Physics in 2014.