Thinking Outside the Die: Trillion Transistor Chips for the ML Accelerator of the Future.

Sean Lie, Cerebras

Sean Lie is co-founder and Chief Hardware Architect at Cerebras Systems. Prior to Cerebras, Sean was a lead architect at SeaMicro and later a Fellow and Chief Data Center Architect at AMD. He holds a BS and MEng in Electrical Engineering and Computer Science from MIT. Sean’s primary interests are in computer architecture and HW/SW codesign.

ML models are growing at an unprecedented rate and traditional forms of scaling chip performance are insufficient to keep up. In this talk, we will examine how co-design can enable specialized ML architectures including wafer-scale chips, sparse computation, optimized memories, and interconnects. We will explore this rich design space using the Cerebras architecture as a case study, highlighting design principles that enable the ML models of the future.

Thinking Outside the Die: Trillion Transistor Chips for the ML Accelerator of the Future.

Speaker

Abstract