November 14, 2018
MTL Seminar Series

xDNN - Xilinx DNN Processor for Deep Convolution Neural Networks

Ashish Sirasao, Xilinx
  • Speaker
  • Abstract
  • Exclusive Content

Ashish Sirasao (M. Tech, EE, IIT Mumbai, 1993) is a Fellow Engineer in the Xilinx Software and IP team. He is currently involved in defining and implementing hardware and software architectures for high-performance accelerators in the area of Deep Learning, Data Analytics, Computer Vision, and Video Codecs on Xilinx FPGAs.

Xilinx DNN processor is a scalable, highly efficient, low latency, and network/model agnostic DNN processor for convolution neural networks.  The presentation provides an overview of the architecture of the DNN processor which include details of DSP Systolic Array, Tensor tiling for efficient data movement, memory architecture for weights and activations and variable bit-precisions support. The presentation also describes the middleware software which includes a compiler, pruning and quantization tools for seamless inference deployment at lower precision, and runtime to enable seamless integration with deep learning frameworks like Tensorflow and Caffe.  The processor runs at 800MHz and is available on a broad range of Xilinx’s 16nm Ultascale+ devices

This content is restricted to our MIG members and members of the MIT community. Login below, or contact us for more information about our partner programs.

Login